The present invention relates generally to the synchronization of two or more systems and more particularly to systems and methods for providing a low noise clock at a remote communication system which closely matches a master reference clock in another system in communication therewith.
In providing wireless communication using radio frequency modulated signals, it is desirable to enable two systems in communication, such as a remote system and a centralized communication hub such as shown in the above referenced patent applications entitled xe2x80x9cSystem and Method for Broadband Millimeter Wave Data Communication,xe2x80x9d to operate tuned to a same RF channel with a certain amount of accuracy in order to provide for reliable acquisition of signal information communicated. Moreover, it is generally desired that the systems and methods utilized to provide this frequency synchronization be able to accommodate frequency drift, or other inaccuracies, associated with design tolerances of components, temperature variations, and/or aging of components as well as to efficiently utilize resources.
Solutions have been developed which attempt to lock up, i.e., automatic frequency compensation (AFC), a remote clock to either a carrier signal that is transmitted from the source or try to lock up to a recovered clock, something that is extracted from the data. For example, one solution has been to use a dotting pattern, i.e., particular bits are placed in the data stream at predetermined positions, in order to allow a remote communication system recover a host clock. A problem with either of these techniques is that they usually provide a very limited lock range, so overall performance due to aging and drift from temperature can be unreliable. As long as the system is properly initialized and running, it will generally operate acceptably within the designed lock range. However, after such a system has been in operation for an extended period of time, it can no longer compensate for drifts beyond some point. Accordingly, if the system requires restarting or reinitialization, especially after the components have aged and thus their operating parameters have drifted, the system may not be able to reacquire the clock signal.
Although it might seem straight forward to enlarge the window of the lock range in which such a system may operate, such an endeavor inevitably leads to a trade off in the frequency characteristics of the system. Specifically, when the lock range over which the clock signal, such as a dotting pattern or the carrier frequency, may be acquired remotely generally results in the increase in phase noise associated with the reference oscillator used, i.e., the effect of the error or noise associated with the frequency versus time characteristics of the oscillator are inversely proportional to the range of frequencies over which the oscillator is used to acquire the signal. Phase noise contributes to the RF carrier through the relation 20 log(RF out frq/base osc freq) At relatively high frequencies, such as the millimeter wave (mmwave) frequencies of the above referenced patent applications entitled xe2x80x9cSystem and Method for Broadband Millimeter Wave Data Communication,xe2x80x9d an even slight increase in phase noise can cause undesired results, such as increased bit error rate (BER).
Moreover, the phase noise characteristics may become even more important in systems utilizing certain relatively high frequency, such as millimeter wave, front ends, such as embodiments shown in the above referenced patent application entitled xe2x80x9cMillimeter Wave Front End,xe2x80x9d wherein a same reference oscillator is utilized for various functions. Where the oscillator output is multiplied up to drive the millimeter wave front end as well as used in signal acquisition at an intermediate frequency, a small increase in phase noise at the oscillator may be unacceptable at the radio frequencies and/or intermediate frequencies used. For example, in a system using a 15 MHZ reference frequency multiplied up to provide a 40 GHz mmwave front end, the phase noise of the reference oscillator is magnified over 2500 times, i.e., 20 log (40 GHz/15 MHz)=20 log (2666)=68.5 dB.
Another solution to providing frequency synchronization between two systems in communication is to provide a very precise oscillator, such as may be tuned and calibrated prior to deployment, in each of the systems in order to ensure that the remote unit will always operate within a selected range of the other system. A very narrow band phase lock loop (PLL) may be employed in such a system to accommodate any small amount of drift associated with such oscillators. However, oscillators which may be relied upon to provide such very precise reference frequencies are generally very expensive and, thus, typically do not provide a desirable alternative.
Other solutions have included the use of a dual mode phase lock loop such that the phase lock loop operates in a wide band mode that can acquire the system signal to some degree and, once it locks in at a course range, narrows the loop bandwidth of the phase lock loop. Such a system relies upon the more fine bandwidth of the second mode of the phase lock loop to filter out phase noise. However, experimentation has revealed that the phase noise associated with the wide lock range of the first mode of the dual modes does not provide a reliable lock, particularly at higher frequencies such as millimeter wave frequencies, from which the second mode may operate.
Accordingly, a need exists in the art for systems and methods providing frequency compensation over a relatively large range of frequencies. Moreover, a need exists in the art for such systems and methods to provide such frequency compensation with a very low phase noise associated therewith.
A further need exists in the art for systems and methods providing remote synchronization using frequency compensation techniques to provide accurate frequency synchronization efficiently. Efficiency considerations include not only the cost of components employed in the frequency compensation techniques, but also the ability to minimize the components used and/or to utilize inexpensive components in other portions of the communication system.
These and other objects, features and technical advantages are achieved by a system and method which provides AFC to provide a low noise clock that very closely matches a master reference clock in another system. According to the preferred embodiment, error between the local clock and the master clock is minimized while a low noise figure is maintained. Moreover, to allow for the use of relatively inexpensive system components, the affects of extreme temperatures, and/or extended operation, the preferred embodiment provides a relatively large, i.e., very tolerant, lock range.
According to a preferred embodiment of the present invention, AFC is provided using a relatively low cost voltage controlled oscillator (VCO), or other controllable oscillator. For example, a preferred embodiment of the present invention uses a Murata TV2178 VCO which is approximately xe2x85x9 the cost of a precision OCXO. However, the Murata part has an aging spec 20 times greater (worse) that a precision part and thus would typically provide a less desirable clock signal.
The oscillator is preferably controllable both to acquire frequency synchronization over a relatively wide range of frequencies and to maintain frequency synchronization during system operation. To accommodate a wide range of offsets between a nominal frequency and the local oscillator, such as the above mentioned VCO, and the master clock to which a matching frequency is sought, a control function is preferably provided, referred to herein as a sweep function, which steps through various operating states of the VCO. This combination produces a very low phase noise clock source that can track frequency offsets automatically with high precision and maintain a wide acquisition range.
Sweep mode is preferably a decision directed control loop. Accordingly, it is better suited to microprocessor control, than a traditional DPLL. The decision that drives the control can be made over very long time intervals and accommodate user intervention more easily, e.g., preferred embodiments of the present invention can differentiate first time installation from an in-service loss of signal, or outage.
In a preferred embodiment, control of the oscillator is provided digitally. For example, a digital to analogue converter (DAC), and digital phase lock loop (DPLL) control circuit are coupled to a VCO of a preferred embodiment to provide control of an oscillator according to the present invention. Accordingly, a low cost oscillator can be augmented with low cost digital components to provide a solution that is less expensive than a high precision, high stability oscillator.
A preferred embodiment of the present invention provides at-least three modes of operation to provide for synchronization of frequencies over a broad range and to maintain synchronization throughout operation. According to a most preferred embodiment, the modes of operation include phase lock loop operation, sweep mode operation, and drift compensation operation. Of course, it should be appreciated that the modes of the preferred embodiment may be used in combination with other operational modes and/or in exclusion of ones of the operational modes described herein.
In the preferred embodiment, during phase lock loop operation, systems of the present invention operate as a typical phase lock loop well known in the art. Accordingly, a signal, such as may be recovered from a receiver, is used as a timing reference and a controllable oscillator, such as a VCO, is adjusted to match a common denominator with the reference signal.
Preferably, phase lock loop functionality is provided digitally (DPLL). The preferred embodiment DPLL calculates a digital value that is written to a DAC for conversion to an analogue voltage for control of the VCO. Preferably, the DPLL control circuit updates the VCO control value very frequently, such as on the order of microseconds. The DPLL also preferably has a lock detect function.
The sweep mode of the preferred embodiment operates to adjust the controllable oscillator to a particular setting, such as by the above described digital control writing a value to the VCO""s control DAC, and then monitors operation of the system, such as to monitor a recovered data signal to identify a specific pattern in the data signal. If monitoring of the system does not indicate a desired result, such as identification of the specific pattern in the recovered data signal, the oscillator is adjusted to a next increment. Operation of the sweep mode to adjust the oscillator preferably includes adjustment both above and below a nominal frequency.
Preferably, monitoring of the system is performed for a preselected amount of time determined to be sufficient to reliably detect the desired condition and brief enough to provide an efficient sweep operation. The selection of operating parameters, such as the incremental size of the oscillator adjustment step, the dwell time, and the range of the steps performed in the sweep mode are preferably dependant on the greater system the AFC circuit is operating within. After the iterative adjustment of the oscillator, the operation of the system is again monitored, continuing as described above until the desired result is detected. Once the system has detected the desired condition, such as a pattern match, it is determined that the oscillator is within the lock range of the PLL and, thus, control is preferably turned over to the above described PLL.
It should be appreciated that operation of the sweep mode as described above allows the use of a narrow band phase lock loop, thus having a low phase noise associated therewith, with a heuristic step approach to provide a wide lock range. Accordingly, an acceptable offset range may be selected with respect to a nominal frequency over which frequency synchronization is to be achieved. This range may be divided into steps, such as incremental steps associated with the lock range of the phase lock loop used. This may, for example, give steps above the nominal frequency and 10 steps below the nominal frequency. Thereafter, the operation of the oscillator and its associated phase lock loop may be swept through these steps, or some subset thereof, sequentially to determine if the phase lock loop is able to achieve a lock at any of these steps.
It shall be appreciated that the sweep mode of the present invention is better suited for applications where a low frequency master clock is utilized with a very high frequency RF, such as in a 40 GHz mm wave system using a 15 MHz IF then is a dual mode PLL. This is because the large multiplicative factor from the reference clock to the RF is too much for even a wide band PLL. In such implementations the IFs are stable and the base clock cannot be recovered reliably.
The drift compensation mode of the preferred embodiment monitors the adjustment values of the oscillator, such as the above mentioned DAC values, while the system is operating. Preferably, while the oscillator is operational under control of the PLL and synchronized with the master clock, the drift compensation mode periodically reads and stores information with respect to the adjustment of the oscillator. It should be appreciated that the control information which achieves a lock in the PLL may vary due to a number of factors, such as local oscillator drift, master clock oscillator drift, thermal drift, and general aging in other reference components in the system, e.g. voltage references. By monitoring and recording the control information of the oscillator during its operation, this information may be utilized as a starting value for functions such as the aforementioned sweep mode. For example, the sweep mode may be required throughout the life of the system for a number of reasons, such as interruption of service due to a service call, a power outage, or any interruption between the master system and the remote system. Additionally, operation of the sweep mode may be required if the PLL becomes unlocked and cannot recover a lock independently.
The oscillator control information monitored by the drift compensation mode may additionally or alternatively be utilized for statistical functions, predictive determinations, alarm conditions, or like control functions. For example, the monitored DAC values may be compared to previous DAC values to determine if the value is drifting over time. Where the drift is determined to be unacceptably rapid or approaching an operational limitation, for example, an alarm condition may be set to forewarn a predicted system malfunction.
A technical advantage of the present invention is that an inexpensive controllable oscillator, such as an inexpensive VCO having a DAC coupled thereto to drive the control voltage, may be utilized to provide reliable remote synchronization of a frequency over a relatively large drift range.
A further technical advantage of the present invention is provided in implementing the AFC with a substantially standard PLL having a very narrow loop bandwidth. This provides a desired low phase noise characteristic in a relatively inexpensive and simple to implement system.
A still further technical advantage is provided by the present invention in a sweep mode operation that allows the oscillator to be stepped through various operating settings and provide the ability to hunt through a given spectrum, such as either side of a selected nominal frequency, for the lock range at which a PLL can then lock onto the master clock.
A yet further technical advantage is provided by the ability of the present invention to provide statistics useful for performance monitoring and trouble shooting.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.